Semiconductor device

ABSTRACT

A semiconductor device is provided which has a driving circuit operable to drive a circuit that has a delay, the semiconductor device including: an auxiliary driving circuit operable to accelerate drive of the driving circuit, which receives a drive signal of the driving circuit as an input signal.

This application is a continuation of U.S. patent application Ser. No.11/678,670, filed Feb. 26, 2007, the entirety of which is incorporatedherein by reference to the extent permitted by law. The presentapplication claims the benefit of priority to Japanese PatentApplication No. 2006-049730 filed in the Japanese Patent Office on Feb.27, 2006, the entirety of which is incorporated by reference herein tothe extent permitted by law.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having a meansfor accelerating drive (or the invention belongs to the field of asemiconductor device).

2. Description of the Related Art

Most of control signals for a solid state imaging device (CMOS imagesensor, CCD), a storage device (SRAM, DRAM, ROM, a flash memory, etc.),a programmable logic array (PLA) and so on are formed from a distributedparameter circuit, and the position of driving circuits is usuallylimited to the end of a control signal line because of its arrangementstructure. Therefore, in the drive of the distributed parameter circuit,the difference in the delay time of the control signals is noticeable.Generally, the driving circuit has an address decoder part foraddressing. The solid state imaging device often has a logic circuitwhich selects operation modes. As shown in FIG. 23, when loads 1015 of adistributed parameter circuit are driven by driving circuits 1020 and1020 disposed at the both ends of the distributed parameter circuit,signal transmission is high speed, but it is necessary to dispose adecoder 1021 and a logic circuit 1022 at both ends, causing thenecessity of a large area. Furthermore, the same signal line is wired atboth ends, which leads to increases in the number of wirings and inpower consumption. On the other hand, as shown in FIG. 24, when loads1015 of a distributed parameter circuit is driven by a driving circuit1020 from one side (for example, see JP-A-2003-143485 (Patent Reference1)), the circuit area can be reduced greatly, but signal delay isnoticeable in a load 1015 on the opposite side of the driving circuit1020 connected, which leads to deteriorated circuit performance.

SUMMARY OF THE INVENTION

In drive on both ends in which a distributed constant load is drivenfrom both ends, high speed signal transmission is realized, but adisadvantage occurs that a large scale address decoder and logic circuitcause an area increase to be noticeable. Furthermore, the same signalline is wired at both ends, which leads to problems of increases in thenumber of wirings and in power consumption. On the other hand, delaytime is noticeable in drive on one side, which leads to a problem ofdeteriorated circuit performance.

Thus, it is desirable to efficiently reduce the circuit scale todecrease delay differences in a circuit for accelerating signaltransmission.

An embodiment of the invention is a semiconductor device having adriving circuit operable to drive a circuit that has a delay, thesemiconductor device including: an auxiliary driving circuit operable toaccelerate drive of the driving circuit, which receives a drive signalof the driving circuit as an input signal.

In an embodiment of the invention, the driving circuit can be arrangedon one side of the circuit that has a delay, and the auxiliary drivingcircuit which accelerates the drive of the driving circuit can bearranged on the other side of the circuit that has a delay. Therefore,the area of the driving circuit is reduced as well as the auxiliarydriving circuit accelerates the drive of the driving circuit, allowingthe implementation of high speed drive of the circuit that has a delay.

According to an embodiment of the invention, the auxiliary drivingcircuit is arranged which accelerates the drive of the driving circuitand receives the drive signal of the driving circuit as an input signal.Therefore, an advantage can be obtained that the drive of the drivingcircuit is accelerated by the auxiliary driving circuit to implement thehigh speed drive of the circuit that has a delay. Furthermore, it isunnecessary to dispose a large scale driving circuit on both ends of thecircuit in order to drive the circuit at high speed, and it issufficient to provide the driving circuit with a large scale area on oneend of the circuit. Therefore, the circuit scale can be drasticallyreduced. As described above, according to an embodiment of theinvention, high speed drive and the reduction in the circuit scale canbe achieved at the same time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram depicting an embodiment of the invention;

FIG. 2 shows a timing chart depicting the operation of an auxiliarydriving circuit according to an embodiment of the invention;

FIG. 3A shows a block diagram depicting an exemplary configuration ofthe auxiliary driving circuit, and FIG. 3B shows a timing chart of theauxiliary driving circuit;

FIGS. 4A and 4B show block diagrams depicting an exemplary configurationof the auxiliary driving circuit;

FIGS. 5A and 5B show block diagrams depicting an exemplary configurationof the auxiliary driving circuit;

FIGS. 6A and 6B show block diagrams depicting an exemplary configurationof the auxiliary driving circuit;

FIG. 7A shows a block diagram depicting an exemplary configuration ofthe auxiliary driving circuit, and FIG. 7B shows a timing chartdepicting the rising edge of the auxiliary driving circuit;

FIG. 8A shows a block diagram depicting an exemplary configuration ofthe auxiliary driving circuit, and FIG. 8B shows a timing chartdepicting the falling edge of the auxiliary driving circuit;

FIGS. 9A and 9B show block diagrams depicting an exemplary configurationof the auxiliary driving circuit;

FIG. 10 shows a block diagram depicting an embodiment of the invention;

FIG. 11 shows a timing chart depicting the operation of the auxiliarydriving circuit shown in FIG. 10;

FIG. 12 shows a block diagram depicting an embodiment of the inventionand a timing chart depicting the operation of the auxiliary drivingcircuit;

FIG. 13 shows a block diagram depicting an embodiment of the inventionand a timing chart depicting the operation of the auxiliary drivingcircuit;

FIG. 14 shows a block diagram depicting an embodiment of the inventionand a timing chart depicting the operation of the auxiliary drivingcircuit;

FIG. 15 shows a block diagram depicting an embodiment of the invention;

FIG. 16 shows a circuit diagram depicting the essential part of theconfiguration shown in FIG. 15;

FIG. 17 shows a timing chart depicting the operation of the auxiliarydriving circuit shown in FIG. 15;

FIG. 18 shows a diagram depicting the relation between the position andthe driving time of the load of the distributed parameter circuitsaccording to an embodiment of the invention and the technique in thepast;

FIG. 19 shows a block diagram depicting an example in which asemiconductor device according to an embodiment of the invention isadapted to a solid state imaging device;

FIG. 20 shows a circuit diagram depicting an exemplary pixel part;

FIG. 21 shows a block diagram depicting an example in which thesemiconductor device according to an embodiment of the invention isadapted to a storage device;

FIG. 22 shows a block diagram depicting an example in which thesemiconductor device according to an embodiment of the invention isadapted to a programmable logic array;

FIG. 23 shows a block diagram depicting the configuration of drive onboth ends in technique in the past; and

FIG. 24 shows a block diagram depicting the configuration of drive onone side in technique in the past.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the invention will be described with reference to ablock diagram shown in FIG. 1.

As shown in FIG. 1, a semiconductor device 1 has a circuit 10 (forexample, a distributed parameter circuit). A driving circuit 20 operableto drive the circuit 10 is connected to one end of the circuit, and anauxiliary driving circuit 30 operable to accelerate the drive of thedriving circuit 20 is connected to the other end of the circuit 10,which receives the drive signal of the driving circuit 20 as an inputsignal. As one example, the auxiliary driving circuit 30 receives thedrive signal of the circuit 10 as an input signal at a level sensecircuit (one of NOT elements) formed of a logic having a logic thresholdVtha, an output signal and an Enable signal of the level sense circuitenter an NAND circuit, and an output signal of the NAND circuit entersthe gate of a MOS transistor to turn to the ON state to rise drive.Furthermore, it receives the drive signal of the circuit 10 as an inputsignal at a level sense circuit (the other NOT element) formed of alogic having a logic threshold Vthb, an output signal and an Enablesignal of the level sense circuit enter a NOR circuit, and an outputsignal of the NOR circuit enters the gate of the MOS transistor turn tothe ON state to fall drive. Here, the auxiliary driving circuit 30 isconnected to one end of the circuit, but it may be connected to anyposition in the circuit, or a plurality of auxiliary driving circuitsmay be disposed. These embodiments will be described later in detail.

As an example, a decoder 21 is connected to the driving circuit 20through a logic circuit 22. The auxiliary driving circuit 30 monitorsthe signal level of a control signal line (the load of the circuit 10)11. When it confirms a transition, it starts driving the control signalline 11. Since the control signal line 11 is a trigger, the decoder andthe logic circuit are unnecessary. In this example, the Enable signalthat is the trigger for the driving circuit 20 is an activation signalfor the auxiliary driving circuit 30. The circuit configuration of theauxiliary driving circuit 30, shown, is an example. Such a circuitconfiguration may be sufficient in which the drive signal is received asthe input signal to accelerate the drive of the driving circuit 20.

Next, FIG. 2 shows a timing chart depicting the operation of theauxiliary driving circuit 30 performed when the circuit 10 is selectedby the decoder 21 and the logic circuit 22. Here, the Enable signal isthe trigger signal for the driving circuit 20. SIGL, SIGM, and SIGR arevoltages at the left end, the center, and the right end of the circuit10, respectively. TRGr and TRGf are voltage of the internal signals ofthe auxiliary driving circuit 30. Vtha and Vthb are logic thresholds forthe logic circuits that receive the control signal line 11 as input.

As shown in FIG. 2, when the Enable signal turns high, the drivingcircuit 20 turns the control signal line 11 to high level. At this time,the drive rises quickly at the left end (the voltage SIGL at the leftend), whereas the drive rises slowly at the center (the voltage SIGM atthe center) and the right end (the voltage SIGR at the right end)because of a distributed constant load. When the signal at the right end(the voltage SIGR at the right end) exceeds the logic threshold Vtha,the internal signal TRGr of the auxiliary driving circuit 30 is changed.Since the Enable signal is high, the auxiliary driving circuit 30supplies high level to the control signal line 11 to accelerate therising signal transition. In addition, the Enable signal turns high, andthus the transistor that supplies the low level of the auxiliary drivingcircuit 30 is forcedly disabled.

When the Enable signal turns low, the low level propagates from the leftend, and at the right end, the level is slowly changed similarly. Atthis time, the transistor that supplies the high level of the auxiliarydriving circuit 30 is forcedly disabled by the Enable signal. When thevoltage SIGR at the right end exceeds Vthb, the internal signal TRGf ofthe auxiliary driving circuit 30 is changed, and the auxiliary drivingcircuit 30 supplies low level to the control signal line 11. Thus, thefalling signal transition is accelerated.

The logic having the control signal line 11 of the auxiliary drivingcircuit 30 as input may share the same circuit both at high level andlow level. However, separation allows each logic level to be madedifferent, which makes a driver that can more efficiently acceleratedrive. For example, the logic threshold Vtha is set low in accelerationof drive at the rising edge, the logic threshold Vthb is set high inacceleration of drive at the falling edge, and thus the timing to drivethe auxiliary driving circuit 30 can speed up at each level. Thedescription of this example will be described later in detail.

Furthermore, the auxiliary driving circuit can be arranged not only forhigh level and low level but also for a plurality of given voltagesupplies. For example, when four types of voltages are supplied, theacceleration driver can be arranged for two types of voltages amongthem. Thus, the efficiency of the circuit area can be increased. Thedescription of this example will be described later in detail.

Next, the auxiliary driving circuit 30 will be described in detail. Inthe description below, the circuit 10 is considered to be a distributedparameter circuit.

FIG. 3A shows the configuration of an auxiliary driving circuit 301which receives the driven signal itself as input for acceleration, andFIG. 3B shows a timing chart depicting the auxiliary driving circuit301.

As shown in FIGS. 3A and 3B, an input IN changes from low level to highlevel, whereby a driving circuit 20 drives a distributed parametercircuit SIG.

When the distributed parameter circuit SIG has a load 15, a delay occursin the signal transition as indicated by a dotted line. When theauxiliary driving circuit 30 is activated by the activation signal ACLEof the auxiliary driving circuit, which switches activation/deactivationof the auxiliary driving circuit 30, the voltage TRG of the internalsignal of the auxiliary driving circuit 30 changes at the time when thedistributed parameter circuit SIG exceeds the logic threshold Vth, andthen the auxiliary driving circuit 30 drives the distributed parametercircuit SIG. Thus, an advantage can be obtained that accelerates thesignal transition of the distributed parameter circuit SIG.

FIGS. 4A and 4B show block diagrams depicting an exemplary auxiliarydriving circuit which accelerates the rising edge, FIGS. 5A and 5B showblock diagrams depicting an exemplary auxiliary driving circuit whichaccelerates the falling edge, and FIGS. 6A and 6B show block diagramsdepicting an exemplary auxiliary driving circuit which accelerates bothof the rising edge and the falling edge.

As shown in FIG. 4A, an auxiliary driving circuit 301 which acceleratesthe rising edge uses an AND logic, configured of an AND circuit whichreceives as input the output signal of a NOT element having the inputsignal SIG from the circuit and the activation signal ACLE of theauxiliary driving circuit, and of a MOS transistor in which the outputsignal is inputted to the gate.

As shown in FIG. 4B, an auxiliary driving circuit 302 which acceleratesthe rising edge is configured in which a NOT element having the inputsignal SIG from the circuit as input is serially connected to a NOTcircuit, the output signal is inputted to the gate of a first MOStransistor, the activation signal ACLE of the auxiliary driving circuitis inputted to a NOT circuit, its output signal is inputted to the gateof a second MOS transistor serially connected to the first MOStransistor, and the first MOS transistor is connected to an input signalline.

As shown in FIG. 5A, an auxiliary driving circuit 303 which acceleratesthe falling edge uses a NAND logic, configured of a NAND circuit whichreceives as input the output signal of a NOT element having the inputsignal SIG from the circuit and the activation signal ACLE of theauxiliary driving circuit, and of MOS transistors in which the outputsignal is inputted to the gate, and one of the MOS transistors isconnected to the input signal line side and the other is grounded.

As shown in FIG. 5B, an auxiliary driving circuit 304 which acceleratesthe falling edge is configured in which a NOT element having the inputsignal SIG from the circuit is serially connected to a NOT circuit, theoutput signal is inputted to the gate of a first MOS transistor, theactivation signal ACLE of the auxiliary driving circuit is inputted to aNOT circuit, its output signal is inputted to the gate of a second MOStransistor serially connected to the first MOS transistor, the first MOStransistor is connected to an input signal line, and the second MOStransistor is grounded.

As shown in FIG. 6A, an auxiliary driving circuit 305 has a level sensecircuit having one logic threshold Vth, which drives both of the risingedge and the falling edge. This auxiliary driving circuit 305 has thecombined function of the auxiliary driving circuit 301 described in FIG.4A and the auxiliary driving circuit 303 described in FIG. 5A,configured to share the level sense circuit formed of NOT elements.

As shown in FIG. 6B, an auxiliary driving circuit 306 has a level sensecircuit having one logic threshold Vth, which drives the rising edge andthe falling edge. This auxiliary driving circuit 306 the combinedfunction of the auxiliary driving circuit 302 described in FIG. 4B andthe auxiliary driving circuit 304 described in FIG. 5B, configured toshare the level sense circuit formed of NOT elements.

Next, the logic threshold Vth which decides the timing of the risingedge and the falling edge will be described.

For example, in the case in which the auxiliary driving circuit 30supports the drive at the rising edge, FIG. 7A shows the configurationin which a logic threshold Vtha of the logic circuit is set low thatreceives the driven signal of an auxiliary driving circuit 30 as input,and FIG. 7B shows a timing chart. The logic threshold Vtha is the logicthreshold that is lower than usual. For example, it is set lower thanthe middle level of ground level (low level) and high level. Inaddition, a dotted line shows the case in which there is no auxiliarydriving circuit.

As shown in FIGS. 7A and 7B, the input IN changes from low level to highlevel to drive a distributed parameter circuit by a driving circuit 20.When the distributed parameter circuit has a load 15, the signaltransition traces a slow rising edge indicated by a dotted line, and adelay occurs. When the auxiliary driving circuit 30 is activated by theactivation signal ACLE of the auxiliary driving circuit which switchesactivation/deactivation of the auxiliary driving circuit 30, the voltageTRG of the internal signal of the auxiliary driving circuit 30 changesat the time when the voltage SIG of the distributed parameter circuitexceeds the logic threshold Vtha, and the auxiliary driving circuit 30changes the voltage SIG of the distributed parameter circuit. The logicthreshold Vtha is set low, that is, it is set to the value closer to lowlevel, whereby the rising edge of the voltage SIG of the distributedparameter circuit can be accelerated. Accordingly, an advantage can beobtained that accelerates the transition of the voltage SIG of thedistributed parameter circuit.

As described above, the logic threshold Vtha is lowered to acquirechanges in the voltage SIG of the distributed parameter circuit drivenat the rising edge by the driving circuit at an earlier point in time,and an advantage can be obtained that accelerates the transition of thevoltage SIG of the distributed parameter circuit.

For example, in the case in which the auxiliary driving circuit 30supports the drive at the falling edge, FIG. 8A shows the configurationin which a logic threshold Vthb of a logic circuit having the drivensignal of an auxiliary driving circuit 30 as input is set higher, andFIG. 8B shows a timing chart. The logic threshold Vthb is a logicthreshold that is higher than usual, and set higher than the middlelevel between ground level (low level) and high level, for example. Inaddition, a dotted line shows the case in which there is no auxiliarydriving circuit.

As shown in FIGS. 8A and 8B, the input IN changes from high level to lowlevel to stop a distributed parameter circuit by a driving circuit 20.When the distributed parameter circuit has a load 15, the signaltransition traces a slow falling edge as indicated by a dotted line, anda delay occurs. When the auxiliary driving circuit 30 is activated bythe activation signal ACLE of the auxiliary driving circuit whichswitches activation/deactivation of the auxiliary driving circuit 30,the voltage TRG of the internal signal of the auxiliary driving circuit30 changes at the time when the voltage SIG of the distributed parametercircuit is equal to the logic threshold Vthb or below, and the auxiliarydriving circuit 30 changes the voltage SIG of the distributed parametercircuit. The logic threshold Vthb is set higher, that is, it is set tothe value closer to high level, whereby the falling edge of the voltageSIG of the distributed parameter circuit can be accelerated.Accordingly, an advantage can be obtained that accelerates thetransition of the voltage SIG of the distributed parameter circuit.

As described above, the logic threshold Vthb is set higher to acquirechanges in the voltage SIG of the distributed parameter circuit drivenat the falling edge by the driving circuit at an earlier point in time,whereby the start of the operation of the auxiliary driving circuit 30can speed up.

Next, FIGS. 9A and 9B show an exemplary circuit in which differentvoltages are provided to the logic threshold Vtha to support the risingedge and to the logic threshold Vthb to support the falling edge.Preferably, setting Vtha to the voltage lower than Vthb sets Vtha to thevoltage closer to low level and sets Vthb to the voltage closer to highlevel, whereby the operations of the configurations described in FIGS.7A, 7B, 8A and 8B can be combined.

As shown in FIG. 9A, an auxiliary driving circuit 307 has two logicthreshold Vtha and logic threshold Vthb, having a level sense circuitwith the logic threshold Vtha, and a level sense circuit with the logicthreshold Vthb in which both of the rising edge and the falling edge aredriven. More specifically, the auxiliary driving circuit 307 has thecombined function of the auxiliary driving circuit 301 described in FIG.4A and the auxiliary driving circuit 303 described in FIG. 5A.

As shown in FIG. 9B, an auxiliary driving circuit 308 has two logicthreshold Vtha and logic threshold Vthb, having a level sense circuitwith the logic threshold Vtha and a level sense circuit with the logicthreshold Vthb in which both of the rising edge and the falling edge aredriven. More specifically, the auxiliary driving circuit 308 has thecombined function of the auxiliary driving circuit 302 described in FIG.4B and the auxiliary driving circuit 304 described in FIG. 5B.

As described above, different voltages are provided to the logicthreshold Vtha to support the rising edge and to the logic thresholdVthb to support the falling edge, whereby the logic threshold Vtha andthe logic threshold Vthb can be set separately. Therefore, both of therising edge and the falling edge can be driven at higher speed.

Next, a semiconductor device having auxiliary driving circuits in whicha plurality of voltages is supplied to a driving circuit and theauxiliary driving circuits perform acceleration in accordance with asingle or a plurality of drives driven by the voltages will be describedwith reference to a circuit diagram shown in FIG. 10 and a timing chartshown in FIG. 11.

As shown in FIG. 10, a semiconductor device 2 has a circuit 10 (forexample, a distributed parameter circuit) that has a load 15. A drivingcircuit 20 which drives the circuit 10 is connected to one end of thecircuit, and a plurality of auxiliary driving circuits 30-1, 30-2 and30-3 which accelerate the drive of the driving circuit 20 is connectedto the other end of the circuit 10 as the auxiliary driving circuitsreceive the drive signal of the driving circuit 20 as an input signal.For the auxiliary driving circuits 30-1 to 30-3, the auxiliary drivingcircuit having the circuit configuration described in FIGS. 4A to 6B,and FIGS. 9A and 9B can be adapted. Furthermore, as an example, adecoder 21 (for example, an address decoder) is connected to the drivingcircuit 20 through a logic circuit 22.

Since the driving circuit drives the load 15 at six types of voltages,V0, V1, V2, V3, V4, and V5, the driving circuit 20 is supplied with aplurality of voltages DRVE0 to DRVE5. Then, only when the drivingcircuit 20 is supplied at voltages V0, V2, and V5, the drive isaccelerated by the auxiliary driving circuits 30-1, 30-2 and 30-3.

As shown in FIG. 11, when the load is separately driven in order ofvoltages DRVE0 (V0), DRVE3 (V3), DRVE1 (V1), DRVE4 (V4), DRVE2 (V2), andDRVE5 (V5), the auxiliary driving circuit 30 reflects the transition ofthe voltage TRGi (TRG0, TRG2, and TRG5) of the internal signal in thedrive of the rising edge or the falling edge of the voltage SIG of thesignal line (for example, a control line of the distributed parametercircuit) only in the case in which the auxiliary driving circuit 30 isactivated at a proper timing with the activation signal ACLEi (ACLE0,ACLE2, and ACLE5) of the auxiliary driving circuit.

The voltage TRGi (TRG0, TRG2, and TRG5) signal of the internal signalwhen the auxiliary driving circuit 30 is activated is indicated by solidlines. A delay is noticeable in the drive at the voltage with noauxiliary driving circuit due to the load of the signal line asindicated by dotted lines. However, in the drive at the voltage with theauxiliary driving circuit 30, changes in the voltage SIG of the signalline are sensed by the logic threshold Vthi (Vth0, Vth2, and Vth5), andthe transition of the voltage SIG of the signal line is accelerated.More specifically, drive is accelerated.

As described above, the auxiliary driving circuit is operated withrespect to a specific voltage that drives the load, whereby theauxiliary driving circuit is activated only when the performance of thecircuit is affected by a delay in particular, for example. The drive isperformed in a normal way other than such drive, whereby the auxiliarydriving circuit can be mounted flexibly in accordance with theproperties and performance of the circuit, and the circuit area can bereduced efficiently.

In the description above, as shown in FIG. 12, the configuration hasbeen described in which in addition to the driving circuit 20 whichdrives the circuit (distributed parameter circuit) 10, the auxiliarydriving circuits 30 are disposed at the right end of the distributedparameter circuit 10. In this configuration, when signals generated by adecoder 21 and a logic circuit 22 propagate through loads 15 of adistributed parameter circuit 10 by a driving circuit 20, a voltage SIGLof a load 15L close to the driving circuit 20 changes at high speed, buta delay might occur in a voltage SIGM of a load 15M in the middle of thedistributed parameter circuit 10, and in a voltage SIMR of a load 15R atthe right end.

Then, an exemplary configuration in which the auxiliary driving circuit30 is provided at the middle point of the distributed parameter circuit10 and at a plurality of points on the opposite side of the drivingcircuit 20 will be described with reference to FIG. 13.

As shown in FIG. 13, in a semiconductor device 3, when a drive signalDRVE of a driving circuit is inputted to a driving circuit 20, a voltageSIGL of a load 15L at the left end of a distributed parameter circuit 10rises. Then, the signal driven at the left end of the distributedparameter circuit 10 propagates through the distributed parametercircuit 10. An auxiliary driving circuit 30-M is activated when avoltage SIGM of a load 15M at the middle point exceeds the logicthreshold Vth, and the voltage SIGM changes to accelerate the drive ofthe load 15M at the middle point. An auxiliary driving circuit 30-R issimilarly activated when a voltage SIGR of a load 15R at the right endof the distributed parameter circuit 10 exceeds the logic threshold Vth,and the voltage SIGL changes to accelerate the drive of the load 15R atthe right end.

In the semiconductor device 3, the auxiliary driving circuit 30-M isprovided at the middle point of the distributed parameter circuit 10,but a plurality of auxiliary driving circuits may be provided at givenpoints in the distributed parameter circuit 10. Particularly, when thedistributed parameter circuit 10 is extremely long, it becomes effectivefor high speed drive to arrange a plurality of auxiliary drivingcircuits at predetermined intervals, for example.

In the configuration in which the auxiliary driving circuit 30 isprovided at a plurality of points, the drive of the distributedparameter circuit 10 is accelerated. Since the auxiliary driving circuit30 can omit the decoder and the logic circuit provided to the drivingcircuit 20, the circuit scale is reduced to decrease the circuit area.In addition, the auxiliary driving circuit can be provided in multiplenumbers at given points in the distributed parameter circuit 10, andthus high speed drive is feasible.

The activation signal ACLE of the auxiliary driving circuit can be thesame as the drive signal of the driving circuit accelerated by theauxiliary driving circuit. An exemplary configuration of this case willbe described with reference to a block diagram and a timing chart shownin FIG. 14.

As shown in FIG. 14, in a semiconductor device 4, a circuit 10 (forexample, a distributed parameter circuit) that has loads 15 is provided.A driving circuit 20 which drives the circuit 10 is connected to one endof the circuit, and an auxiliary driving circuit 30 which acceleratesthe drive of the driving circuit 20 is connected to the other end of thecircuit 10, as the auxiliary driving circuit receives the drive signalof the driving circuit 20 as an input signal. For the auxiliary drivingcircuit 30, the auxiliary driving circuit having the circuitconfiguration described in FIGS. 4A to 6B, and FIGS. 9A and 9B can beadapted. Furthermore, as an example, a decoder (an address decoder) 21is connected to the driving circuit 20 through a logic circuit 22.

To the auxiliary driving circuit 30, an activation signal ACLE issupplied which switches whether the auxiliary driving circuit 30 isactivated or deactivated. The activation signal ACLE can be the same asa drive signal DRVE of the driving circuit 20. Therefore, the auxiliarydriving circuit 30 is activated while the drive signal DRVE is beinginputted.

As described above, the control signal for the driving circuit 20 andthe auxiliary driving circuit 30 is made in common, whereby the numberof the control signals can be reduced, and the simplification of thetiming of control and the simplified control over the circuit arefeasible.

The auxiliary driving circuit which accelerates the drive describedabove monitors the signal transition of the load of the distributedparameter circuit driven on one side, and autonomously accelerates thedrive. Most of the address decoder and the logic circuit are omitted,and the drive at the speed near the drive on both ends can be realizedwith a small area. However, in the case in which it is necessary to setbuffer voltage at the falling edge of the pulse like a CMOS imagesensor, it is sometimes difficult to design a plurality of thresholdlogics.

For example, in a solid state imaging device in which it is necessary todrive from −1 V to 3.3 V the gate electrode of a transfer transistorwhich is arranged in the unit pixel of the solid state imaging device innegative voltage drive, the gate electrode is sometimes driven through 0V at the time when it falls from 3.3 V to −1 V. An exemplaryconfiguration which implements this will be described with reference toa block diagram shown in FIG. 15, a circuit diagram shown in FIG. 16,and a timing chart shown in FIG. 17.

As shown in FIG. 15, in a semiconductor device 5, a circuit 10 (forexample, a distributed parameter circuit) that has loads 15 is provided.A driving circuit 20 which drives the circuit 10 is connected to one endof the circuit, and an auxiliary driving circuit 30 which acceleratesthe drive of the driving circuit 20 is connected to the other end of thecircuit 10, as the auxiliary driving circuit receives the drive signalof the driving circuit 20 as an input signal. The auxiliary drivingcircuit 30 monitors the signal transition of the loads 15 of the circuit10, having a level sense circuit 31 formed of a logic with a logicthreshold, and a flag memory 40 which temporarily stores the state ofaccelerated drive, in which each output of the level sense circuit 31and the flag memory 40 is used for determining the drive to drive theloads 15. Furthermore, a decoder 21 is connected to the driving circuit20 through a logic circuit 22, for example.

In the semiconductor device 5, the signal level of the loads 15 of thedistributed parameter circuit changed by the driving circuit 20 ismonitored, and the auxiliary driving circuit 30 accelerates the drivewhen a transition occurs. At this time, the flag memory 40 stores theevent that drive is generated. The drive at the falling edge isdetermined in accordance with the state of the flag memory 40, and it isdriven by the auxiliary driving circuit 30. The order of operation ofthe rising edge and the falling edge may be reversed.

Next, an exemplary circuit of the auxiliary driving circuit 30 will bedescribed with reference to FIG. 16, and the operation of the auxiliarydriving circuit 30 will be described with reference to a timing chartshown in FIG. 17. In addition, a dotted line in FIG. 17 shows the casein which there is no auxiliary driving circuit.

As shown in FIGS. 16 and 17, an auxiliary driving circuit 30 is the sameas those described in FIGS. 1 and 9. As compared with the case in whichthere is no auxiliary driving circuit, for the voltage SIG of the loadof the distributed parameter circuit, the auxiliary driving circuit 30is used to accelerate the rising edge of the voltage SIG foraccelerating the drive at the time when the rising edge exceeds acertain level, for example, at the time when it exceeds the logicthreshold Vth. At this time, a flag memory 40 stores the driving state,and an intermediate voltage Vmid is supplied by XPmid which suppliesbuffer voltage to a driver 45 for transient voltage. The flag memory 40is reset at the timing that Vss of off voltage is supplied to XPlow, anda level sense circuit 31 automatically falls to the OFF state to end thesequence of pulse drive. Flg in the drawing indicates the output voltageof the flag memory 40. Furthermore, the auxiliary driving circuit 30 hasthe driver 45 for transient voltage which temporarily stores apredetermined voltage when the load falls, and then to whichintermediate voltage is supplied when falling.

In the semiconductor device 5, attention is focused on the signal linewhich changes to high level right before it needs the supply of bufferpotential. When the auxiliary driving circuit 30 accelerates the highlevel drive, the flag memory 40 is written, and then it is determinedthat buffer voltage is supplied. The flag memory 40 is reset when thelow level drive is accelerated through buffer voltage, and the statereturns to the original state. More specifically, since one logicthreshold Vth at the rising edge is set to automatically set theconditions to generate the falling edge, it is unnecessary to set thelogic threshold at the falling edge. As described above, an advantage ofpackaging density can be obtained by the reduction in the area while thedrive characteristics near the drive at both ends are realized.

Next, the simulation results in which the distributed parameter circuitsare driven in the configuration of acceleration drive by thesemiconductor device 1 described in FIG. 1, the configuration of driveon both ends and the configuration of drive on one side in technique inthe past described in FIGS. 23 and 24 will be described with referenceto FIG. 18. In FIG. 18, the driving time is represented on the verticalline, and the position of the load in the distributed parameter circuitis represented on the horizontal line. In addition, the number of theloads of the distributed parameter circuit in each of the semiconductordevices was 1024 loads. In the drive on one side, the driving circuitwas arranged on the left side of the distributed parameter circuit. Inthe drive on both ends, the driving circuit was arranged on the bothends of the distributed parameter circuit. In the semiconductor deviceaccording to an embodiment of the invention (acceleration drive), thedriving circuit was arranged on the left side of the distributedparameter circuit, and the auxiliary driving circuit was connected onthe right side of the distributed parameter circuit. In addition, thesize of the drive transistor was all the same.

As shown in FIG. 18, in the semiconductor device in the drive on oneside, the delay time is noticeably prolonged at the position separatedfrom the driving circuit, whereas in the semiconductor device with theauxiliary driving circuit, it has the delay characteristics near thedrive on both ends, and the drive is more significantly accelerated thanthe drive on one side. Furthermore, an advantage of reduction in thecircuit area in drive on both ends is as discussed above. As describedabove, the configuration in which the auxiliary driving circuit isarranged is significantly effective for efficiently reducing the circuitscale, and for decreasing differences in delay in the circuit foracceleration.

Next, an exemplary configuration in which the semiconductor deviceaccording to an embodiment of the invention is a solid state imagingdevice will be described with reference to a block diagram shown in FIG.19 and an enlarged diagram shown in FIG. 20. In FIG. 19, as an example,a MOS image sensor is shown.

As shown in FIG. 19, in a semiconductor device (solid state imagingdevice) 6, pixels 51 are arranged two dimensionally in a matrix in thevertical direction (x direction) and the horizontal direction (ydirection). Each of the pixels 51 in the pixel row is connected andcontrolled by a control signal line 52.

The MOS image sensor has a pixel array part 50 in which the pixels 51including a photoelectric conversion element are arranged twodimensionally in a matrix, and as peripheral circuits, a driving circuit20 which drives the control signal line 52, a logic circuit 61 whichcontrols the driving circuit 20, a vertical scanning circuit 62, atiming generating circuit (not shown), and a horizontal scanning circuit63. To the MOS image sensor, auxiliary driving circuits 30 whichaccelerate the drive with the drive signal as an input signal areconnected to the opposite side on which the logic circuit 61 of thecontrol signal line 52 is connected. For example, for the control signalline 52, there are a transfer control line 112, a reset control line 113and a selection control line 114. Therefore, the auxiliary drivingcircuit 30 is connected to each of the transfer control line 112, thereset control line 113 and the selection control line 114.

In the configuration, a row selected by the vertical scanning circuit 62and the logic circuit 61 is driven by the driving circuit 20 from oneside. Since the auxiliary driving circuits 30 are arranged on theopposite side, the drive of the control signal line (horizontal signalline) 52 for the row driven by the driving circuit 20 can beaccelerated.

Furthermore, an output signal line 111 is wired to every column withrespect to the matrix array formed of the pixels 51 in the pixel arraypart 50. Moreover, to each of the pixels 51, a reset line 115 is wiredwhich supplies reset voltage.

An exemplary circuit configuration of the pixel 51 will be describedwith reference to an enlarged diagram shown in FIG. 20. The unit pixelof this exemplary circuit has a photoelectric conversion element, aphotodiode 511, for example, configuring a pixel circuit including fourtransistors, a transfer transistor 512, a reset transistor 513, anamplifier transistor 514 and a selection transistor 515, for example.Here, an N channel MOS transistor is used for the transfer transistor512, the reset transistor 513, the amplifier transistor 514 and theselection transistor 515, for example.

The transfer transistor 512 is connected between the cathode electrodeof the photodiode 511 and a floating diffusion part 516 which is acharge voltage converting part, in which a transfer pulse TRG is appliedto the gate electrode (control electrode) to transfer signal electriccharge (here, electrons) that is photoelectrically converted by thephotodiode 511 and stored here to the floating diffusion part 516.

In the reset transistor 513, the drain electrode is connected to thereset line 115, and the source electrode is connected to the floatingdiffusion part 516, in which prior to the transfer of the signalelectric charge from the photodiode 511 to the floating diffusion part516, a reset pulse RST is applied to the gate electrode to reset thepotential of the floating diffusion part 516 to a reset voltage Vrst.

In the amplifier transistor 514, the gate electrode is connected to thefloating diffusion part 516, and the drain electrode is connected to thepixel source Vdd, in which the potential of the floating diffusion part516 after reset by the reset transistor 513 is outputted as reset level,and the potential of the floating diffusion part 516 to which the signalelectric charge has been transferred by the transfer transistor 512 isoutputted as signal level.

For example, in the selection transistor 515, the drain electrode isconnected to the source electrode of the amplifier transistor 514, andthe source electrode is connected to the output signal line 111, inwhich a selection pulse SEL is applied to the gate electrode to turn tothe ON state and to turn the pixel 51 to the selected state, and asignal outputted from the amplifier transistor 514 is outputted to theoutput signal line 111. In addition, for the selection transistor 515,such a configuration may be adopted that the selection transistor 515 isconnected between the pixel source Vdd and the drain electrode of theamplifier transistor 514.

Furthermore, returning to FIG. 19, the description will be continued.The driving circuit 20 is configured to perform the read operation whichreads the signal of each of the pixels 51 in the read row of the pixelarray part 11.

The vertical scanning circuit 62 is configured of a shift register or anaddress decoder, for example, in which the reset pulse RST, the transferpulse TRG and the selection pulse SEL are properly generated to scaneach of the pixels 51 of the pixel array part 10 in the electronicshutter row and the read row in units of rows vertically (in thevertical direction), at the same time, the electronic shutter operationis performed to sweep the signal of the pixel 51 in the row with respectto the electronic shutter row. Then, the electronic shutter operation isperformed with respect to the same row (electronic shutter row) the timeperiod corresponding to the shutter speed before read scanning isperformed by the driving circuit 20.

The horizontal scanning circuit 63 is configured of a shift register oran address decoder, for example, which horizontally scans at every pixelcolumn of the pixel array part 10.

According to the semiconductor device 6 (solid state imaging device),the auxiliary driving circuits 30 are arranged on the opposite side ofthe driving circuits 20 of the control signal line 52, whereby theportions of the vertical scanning circuit and the logic circuit can beomitted on the side on which the auxiliary driving circuits 30 arearranged. Therefore, an advantage of reduction in the circuit area canbe obtained as well as the drive speed can be accelerated by theauxiliary driving circuit 30 and the delay distribution of theaccelerated horizontal signal line can be uniformized, contributing tothe improvement of performance of the solid state imaging device.Similar advantages can be obtained in the similar configurations notonly in the CMOS image sensor but also in the drive of the horizontalsignal line of a CCD.

Next, an exemplary configuration in which the semiconductor deviceaccording to an embodiment of the invention is a storage device will bedescribed with reference to a block diagram shown in FIG. 21. In FIG.21, as an example, a dynamic random access memory (DRAM) is shown.

As shown in FIG. 21, a semiconductor device (storage device) 7 has anarray in which a memory element with a single transistor and a singlecapacitor is arranged in an array vertically and horizontally. A wordselection circuit 71 selects a word selection line 72, and the line isdriven by a driving circuit 20 to write or read data in a predeterminedstorage element 73.

An auxiliary driving circuit 30 is arranged on the opposite side end towhich the driving circuit 20 on the word selection line 72 is connected.For example, for the auxiliary driving circuit 30, the auxiliary drivingcircuits in the configurations described in FIGS. 4A to 6B, and FIGS. 9Aand 9B can be used. In the storage element 73, the word selection line72 is connected to the gate of a MOS transistor 74, a bit line 75 isconnected to one side of the MOS transistor, and a capacitor 76 isconnected to the other side. In the storage device 7, the auxiliarydriving circuit 30 accelerates the drive of the word selection line 72.

In the write operation, voltage is applied to the word selection line 72which is to select a row, data is passed to the corresponding bit line75, and then the row is selected to apply voltage to the gate of the MOStransistor 74. Thus, information is stored in the capacitor 76 of thecell in which the source and drain of the MOS transistor 74 areconducting.

In the read operation, first, the bit line 75 is set to the same voltageas a pre-charge power line (not shown). The voltage of the pre-chargepower line is set to the threshold voltage of a sense amplifier.Subsequently, the pre-charge switch is turned off, and the voltagepre-charged in the bit line 75 is retained for a while. Then, the wordselection line 72 is selected to apply voltage. Thus, the source anddrain of the MOS transistor 74 are conducted to pass information in thecapacitor 76 to the bit line 75. Since the bit line 75 has pre-chargevoltage, it becomes a voltage value exceeding the threshold voltage whenthe capacitor 76 has electric charge, whereas it becomes a voltage valuebelow the threshold voltage when it has no electric charge. Here,voltage is applied to the control terminal of the sense amplifier toactivate the sense amplifier, and the voltage value of the bit line 75is changed to the voltages corresponding to “1” and “0” with referenceto the threshold voltage. At this time, the same data is again stored inthe capacitor 76 of the memory cell. Finally, the column selectionswitch is turned to the ON state to output information in the bit line75.

According to the semiconductor device 7 (storage device), the auxiliarydriving circuit 30 is arranged on the opposite side of the drivingcircuit 20 of the word selection line 72, whereby the word selectioncircuit 71 can be omitted on the side on which the auxiliary drivingcircuit 30 is arranged. Therefore, the advantage of reduction in thecircuit area can be obtained, as well as the drive speed can beaccelerated by the auxiliary driving circuit 30 and the delaydistribution of the accelerated horizontal signal line can beuniformized, contributing to the improvement of the read rate and writerate of the storage device.

Next, an exemplary configuration in which the semiconductor deviceaccording to an embodiment of the invention is a storage device will bedescribed with reference to a block diagram shown in FIG. 22. In FIG.22, as an example, a programmable logic array configured of a PLA(Programmable Logic Array) formed of a dynamic logic circuit is shown.

As shown in FIG. 22, a semiconductor device (programmable logic array) 8is a PLA (Programmable Logic Array) formed of a dynamic logic circuit.It is considered that a driving circuit 20 turns all the outputs to lowlevel when it is deactivated by a drive signal DRVE. After pre-chargedby a PRE signal, when an input from the logic circuit 22 in the previousstage is determined, the driving circuit 20 is activated by the drivesignal DRVE of the driving circuit 20. When the auxiliary drivingcircuit 30 is activated by the activation signal ACLE of the auxiliarydriving circuit 30, the transition at the rising edge can beaccelerated.

According to the semiconductor device (programmable logic array) 8, thedrive of the programmable logic array can be accelerated. Particularly,since it is generally difficult to form the configuration of the driveon both ends because of the flow of logic computation, the semiconductordevice provides the advantage that accelerates the signal line that isformed of the distributed parameter circuit.

The semiconductor device according to an embodiment of the inventionserves for reduction in the area as well as for acceleration of thedriving circuit for the control signal line with the distributedparameter circuit as a load, including a solid state imaging device suchas a CMOS image sensor and a charge coupled device (CCD), a storagedevice such as a dynamic random access memory (DRAM), a static randomaccess memory (SRAM), a read only memory (ROM), and a nonvolatilememory, and a programmable logic array such as PLA.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

1. A semiconductor device comprising: a driving circuit operable todrive a circuit that has a delay; an auxiliary driving circuit operableto accelerate the drive of the driving circuit the auxiliary drivingcircuit is configured to receive a drive signal of the driving circuitas an input signal and monitors signal transition of the circuit,wherein, the auxiliary driving circuit includes a logic circuit whichreceives the input signal, the logic circuit having logic with athreshold associated with a rising edge of the drive that is differentfrom a threshold associated with a falling edge of the drive.
 2. Thesemiconductor device according to claim 1, wherein the thresholdassociated with the rising edge is lower than the threshold associatedwith the falling edge.
 3. The semiconductor device according to claim 2,wherein the threshold of drive at the rising edge is lower than a middlelevel of a low level and a high level and the threshold of drive at thefalling edge is higher than the middle level of the low level and thehigh level.